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rileyesi
Joined: 19 Dec 2006
Posts: 398
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 Posted: Tue Dec 02, 2008 8:08 pm Post subject: ADC Input Impedence Limit? |
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Hi,
I am using the Mega8 chip. The datasheet says:
| Quote: |
The ADC is optimized for analog signals with an output impedance of approximately 10 kΩ or
less. If such a source is used, the sampling time will be negligible. If a source with higher impedance
is used, the sampling time will depend on how long time the source needs to charge the
S/H capacitor, with can vary widely. The user is recommended to only use low impedant sources
with slowly varying signals, since this minimizes the required charge transfer to the S/H
capacitor.
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I am reading 4 voltages about 10 times per second (so, 40 conversions per second). The ADC is in single mode and the chip is driven by 4.0 MHz external oscillator.
Is there a way to calculate how using a higher input impedence (like, say 15k) will change the sampling time?
Also, what scale of magnidude are we talking about when they say that the sampling time may increase? Are we talking microseconds? Maybe I am worring needlessly!
I put in a tech request to Atmel, but they are sometimes slow to respond.
As always, Thanks and Regards,
Pete |
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rileyesi
Joined: 19 Dec 2006
Posts: 398
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| Posted: Tue Dec 09, 2008 8:20 pm Post subject: |
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As a follow up, here is what I got back from Atmel
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If you want to connect a circuit like high resistance potentiometer to the ADC pins of ATmega8,
the equivalent resistance of this potentiometer should better less than 10K ohm. If a source with
higher impedance is used, the sampling time will depend on how long time the source needs to
charge the S/H capacitor, witch can vary widely. In your case, 15kOhm should probably be ok
when sampling 10 times/second, but the best is for you to try this out in your application. If it does
not work, I suggest you to add a voltage buffer between the potentiometer and the ADC pins of
ATmega8.
Best Regards,
Atmel Technical Support Team
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So, the answer is "try it and see"! By the way, I did and there are no problems.
Hope this helps someone!
Pete |
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AdrianJ
Joined: 16 Jan 2006
Posts: 2483
Location: Queensland
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| Posted: Mon Dec 15, 2008 7:39 am Post subject: |
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Design by guesswork !
The Atmel datasheet does specify a nominal value of 14pf for the sample and hold capacitor, although they say it varies 'widely'. But as long as you then swamp this value with a capacitor say 1000 times bigger than this to ground, then the S&H circuit cannot have an error bigger than 0.1 %, regardless of the source resistance. So for example 22 nf ought to be plenty. Then you can work out how fast your source impedance can change the voltage across this capacitor. This will tell you the max slew rate on the input you can measure, at 0.1% accuracy.
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Adrian Jansen
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Visovian
Joined: 31 Oct 2007
Posts: 584
Location: Czech
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| Posted: Wed Dec 17, 2008 12:08 pm Post subject: |
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| Quote: | | Is there a way to calculate how using a higher input impedence (like, say 15k) will change the sampling time? |
Let us do some math.
The voltage on the sample condensator will be 99.96% of measured voltage
in time 8*R*C. I think it is sufficient accuracy, but maybe
the real time in the chip is longer.
So if C=14 pF and R = 15000 Ohm
then R*C=0.21 microsec, 8*R*C=1,68 microsec.
It can be seen that for example if we use
30 kOhm instead 15 kOhm, the pure time for loading
the condensator will grow from 1.68 to 3.36 microsec.
But this is only theory, the real process is probably more complex. |
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AdrianJ
Joined: 16 Jan 2006
Posts: 2483
Location: Queensland
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| Posted: Wed Dec 17, 2008 10:34 pm Post subject: |
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Good analysis. Thats the input side, and shows that input inpedance around 10-20 K is fine.
But if the ADCs are anything like the Texas ones ( for which they show how the capacitor switching works ), then when the ADC sample is taken, that 14 pf cap is discharged. So you need to supply a low enough impedance on the input to hold up the voltage so it does not change over the sampling interval. Maybe the Atmel ones are not like that, but I always found I got better stability with around 10-100 nf on the inputs, ie using the input cap to provide a low impedance path to the sample and hold circuit.
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Adrian Jansen
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Visovian
Joined: 31 Oct 2007
Posts: 584
Location: Czech
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| Posted: Thu Dec 18, 2008 8:08 am Post subject: |
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Hi,
I tkink, using capacitor 10 - 100nF on ADC input is a very good idea.
It has the similar effect as if the output impedance of source was greater.
It can also filter various spikes etc.
It is suitable for DC measuring when the voltage does not change in time too fast.
Otherwise our capacitor would no be able to folow the source voltage. |
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mhe
Joined: 23 Dec 2008
Posts: 13
Location: mashhad
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| Posted: Fri Jan 23, 2009 6:52 am Post subject: ADC Input Impedence Limit? |
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Hi 
I have a question of AREF Atmega32.
how much the more lorgest voltege AREF ? 
thank you . 
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Best Regards .
M - H |
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AdrianJ
Joined: 16 Jan 2006
Posts: 2483
Location: Queensland
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| Posted: Mon Jan 26, 2009 11:16 pm Post subject: |
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The datasheet for the AtMega32 will tell you the full details. But in general ARef cannot be larger than the chip supply voltage to Vcc and AVcc.
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Adrian Jansen
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