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albertsm
Joined: 09 Apr 2004 Posts: 5913 Location: Holland
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Posted: Sat Jun 11, 2022 10:09 am Post subject: |
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ubrr is not defined. since normally it is not required.
but you can add it :
- look for the [WIO] section
- you will notice UBRR and UBRR0 that point the LSB of the word register.
- you can add : UBRR1 and point to its LSB with is $CC
when reading/writing to 16 bit hardware registers you should always let the compiler handle it.
reading is mostly done by reading LSB first, then MSB
writing is done by MSB first, then LSB
but... this varies. xmega does this different and so does new platforms like xtiny,megax and avrx
you should also always check the datasheet since some processors share the MSB of the baud register with some other settings. mostly older chips. _________________ Mark |
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MWS
Joined: 22 Aug 2009 Posts: 2262
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Posted: Sat Jun 11, 2022 11:06 am Post subject: |
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njepsen wrote: | I am also getting some confusing results from setting UBRR and its siblings. | I'm confused about your confusion.
Quote: | UBRR1 = const[/code] is not accepted by the compiler. I note that there is no entry in the m1284p.def for UBRR1. | The entry UBRR1 = $cc below section [WIO] is missing. Add it and you're ok.
Quote: | Also - for example is accepted, but only the LS byte is loaded it seems, so if i run this in the 1284p, and then read UBRR0 and UBRR0L the result is consistent | I would suggest the word-creation nonsensistent.
You load a 9bit value into an 8bit register, the compiler will correctly create an 8bit write, thus you load UBRR0L with the (overflown and truncated) value of: 1
It would be fatal, if the compiler would work the other way by using the source variable's width to decide the type of bit transfer.
Quote: | only the LSB is set which I would expect. I cant check this with UBRR1 because it won't compile. | This is partly not correct.
Only the definition for UBRR1 is missing, but UBRR1H exists within the dat-file. If you want to check whether your overflown write affects the higher UBR-register, you can do so by reading UBRR1H.
Quote: | I can also write to and read UBRR | UBRR is the same as UBRR0. This abbreviation belongs to ages, where Atmels only sported one USART, in the dat-file all point to the same IO-address:
Code: | [IOEXT]
UBRR0L = $c4
UBRR = $C4
[WIO]
UBRR0 = $c4 | Same is valid for UDR and UDR0 for example.
Quote: | Code: |
UBRR = 257
print #1,UBRR0
print #1,bin(UBRR0) ' -> 0000000000000001
print #1,bin(UBRR) ' -> 0000000000000001
print #1, bin(UBRR0L) ' -> 00000001
stop | and the result is the same as writing to UBRR0 Code: |
UBRR0 = 257
print #1,UBRR0
print #1,bin(UBRR0) ' -> 0000000000000001
print #1,bin(UBRR) ' -> 0000000000000001
print #1, bin(UBRR0L) ' -> 00000001 |
confusing | If your brain runs in circles over such bric-à-brac, you'll never get your code done |
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njepsen
Joined: 13 Aug 2007 Posts: 469
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Posted: Sat Jun 11, 2022 11:23 pm Post subject: |
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Quote: | As written, you confuse sample rate with sample rate prescaler. |
I'm not sure this is correct. Sure - clock recovery is sampled 8 or 16 times, but so is received data. From the data sheet section 21.4.2 Quote: |
However in this case the receiver will only use half the number of samples (reduced from 16 to 8) for data sampling and clock recovery and therefore a more accurate baud rate setting and system clock are required when this mode is used. For the transmitter there are no downsides. |
Corollary: for the receiver there are downsides.
When they talk about 'data sampling' , received data is referred to. In section 21.9.2, it states clearly that "DATA SAMPLING" is halved when U2X is set. _________________ Neil |
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MWS
Joined: 22 Aug 2009 Posts: 2262
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Posted: Sun Jun 12, 2022 12:43 am Post subject: |
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njepsen wrote: | therefore a more accurate baud rate setting and system clock are required | Which for the first part you achieve by a lower error by setting U2X.
Quote: | When they talk about 'data sampling' , received data is referred to. In section 21.9.2, it states clearly that "DATA SAMPLING" is halved when U2X is set. | Means data sampling is more coarse and has more chance of a miss at closer fitting baud rates, while being finer at higher errors.
Considering the quote above about accurate baud rate settings, I'd say the option to chose is obvious.
Quote: | Corollary: for the receiver there are downsides. | Which will only show up, if the connected hardware's baud rate is off-center.
Imagine an error of +3% with and +6% without U2X, then assume your connected hardware is off for +4.5%, 1.5% error in each direction.
Only in this case I can imagine a benefit of having more samples by U2X = 0. |
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njepsen
Joined: 13 Aug 2007 Posts: 469
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Posted: Sun Jun 12, 2022 10:24 pm Post subject: |
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So we are agreed that the data sampling rate is also affected? I agree with your views re baud rate, but you have overlooked the question of noise immunity, for which we have tools such as parity and CRC ( and slower baud rates of course). I'm not convinced that lowering the DATA sample rate doesn't have downsides.
Quote: |
PostPosted: Sat J
If your brain runs in circles over such bric-à-brac, you'll never get your code done
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The devil is in the detail MWS and I don't accept criticism for looking at the detail. _________________ Neil |
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MWS
Joined: 22 Aug 2009 Posts: 2262
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Posted: Mon Jun 13, 2022 5:45 pm Post subject: |
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njepsen wrote: | So we are agreed that the data sampling rate is also affected? | Sure, it has to, the system clock is the limit.
Look up for example the baud-rate table for 8MHz in the data sheet, and look for UBRR = 0 (baud rate prescaler 1).
You'll find 500kbaud without U2X (ratio sys-clock vs baud = 16) and 1Mbaud with U2X (ratio 8), that's where the 8 and 16 in the baud rate equation are coming from.
Quote: | but you have overlooked the question of noise immunity | If this allegation is rhetorical, then I'd say: You can't know, maybe I've thought about that.
If your allegation has to be taken literally, then I say: Surly not, first mentioning of the word "noise" was in your latest message and otherwise not discussed.
The data sheet does not go too much in detail about noise, but so far:
Quote: | Higher error ratings are acceptable, but the Receiver will have less noise resistance when the error ratings are high, especially for large serial frames | Definitely speaks for using U2X = 1, as error rates are consistently lower and long frames better match.
Also notice in the data sheet how levels are sampled by 4, 5, 6 for U2X = 1, and 8, 9, 10 for U2X = 0.
For mode 4, 5, 6 every bit is sampled over a width of 0.375, while 8, 9, 10 samples for 0.1875.
By itself width does not affect noise immunity, the probability of surges exactly while the three samples are under way, will be equal among modes.
However it will affect longer frames if baud rate error is not zero, as then the consecutive offset adds up, till two samples are cross-border to the next bit and a fault happens. As more samples are offset near bit-edge, as more any noise will have effect.
What we can learn is, that at >0% baud rate error it is crucial for improving noise immunity, tadaaa: shorter frames.
Quote: | I'm not convinced that lowering the DATA sample rate doesn't have downsides. | Luckily I do not have to convince you, it seems we are far away and thus I very likely have not to suffer from effects if things blow up.
Also do not mistake my extensive reply as attempt to convince you - I simply had fun to think it out.
Quote: | The devil is in the detail MWS and I don't accept criticism for looking at the detail. :D | Your work benefits surely if you look at details, my criticism was directed to your use of fairy dust code, and worse, you've used cheap one. |
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