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sentinel
Joined: 02 Feb 2009 Posts: 141 Location: Tasmania
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Posted: Thu Jan 20, 2022 4:01 pm Post subject: |
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I think I need to change the oscillator frequency to 1MHz and in future change to the Picopower version which will allow setting of the BODS feature.
I still don't know why the chip resets when coming out of Powersave with BOD set at 1.8V, as the supply voltage never drops below about 2.6V, even after half an hour. |
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SZTRAD
Joined: 30 Dec 2019 Posts: 165
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Posted: Thu Jan 20, 2022 4:14 pm Post subject: |
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And you're sure it's resetting?
Doesn't look like a reset to me.
Turn off the BOD on powersave. |
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O-Family
Joined: 23 May 2010 Posts: 320 Location: Japan
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Posted: Fri Jan 21, 2022 1:24 am Post subject: |
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Is the fuse bit of [WDTON] set to [1]?
BASCOM sets the watchdog timer to the minimum time on reset.
Why does the watchdog interrupt start at 0?
The [Power_on] signal is set as a pin change interrupt, and the processing routine should return without doing anything.
In the main routine, set the AVR to power save when [Power_on] is off, and when [Power_on] is turned on, the interrupt will start the AVR.
It will consume more power, but as a safety measure, the watchdog can be activated, so that the interrupt handling routine returns without doing anything as well as the [Power_on] signal, and the AVR is activated from power save to do the same in the main routine.
I have no trouble with this kind of system. |
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sentinel
Joined: 02 Feb 2009 Posts: 141 Location: Tasmania
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Posted: Fri Jan 21, 2022 3:47 am Post subject: |
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No, the watchdog fuse bit is not set when flashing the device. The same thing can be done in software, can't it?
"BASCOM sets the watchdog timer to the minimum time on reset." I was not aware of this. But surely the !jmp $0000 instruction will not change the watchdog timer value?
"Why does the watchdog interrupt start at 0?" I wanted to save the current date and time from the RTC before restarting the program. I did this in the watchdog isr.
I will use your suggestion of a pin change interrupt in the redesign. I can connect Int0 to the connection status pin of the Blutooth module which toggles at 1Hz, so that when power is restored, the toggling will wake the micro. The BT module is not backed up by battery, so will only provide that wake-up signal when power is restored.
SZTRAD, the reset only happens when the BOD is set. With the BOD fuse bit disabled, the micro comes out of Powersave nicely. The 168A does not allow disabling the BOD in software. |
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SZTRAD
Joined: 30 Dec 2019 Posts: 165
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Posted: Fri Jan 21, 2022 7:35 am Post subject: |
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Hi
yes you are right this mode allows up to 168P.
Sorry |
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O-Family
Joined: 23 May 2010 Posts: 320 Location: Japan
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Posted: Fri Jan 21, 2022 10:04 am Post subject: |
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Yes, if the [WDTON] fuse bit is [1], the watchdog timer will stop at reset.
If the [WDTON] fuse bit is [0], BASCOM sets the watchdog timer to the shortest 16ms.
For programs that take a long time from AVR reset to watchdog reset (eg LCD initialization routines), the watchdog will occur forever and appear to freeze.
This symptom was similar to that of your system. |
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SZTRAD
Joined: 30 Dec 2019 Posts: 165
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Posted: Fri Jan 21, 2022 10:31 am Post subject: |
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Hi
Well, I agree with you, but it would always behave the same for all boards. Not just one out of 10 as he says. |
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MWS
Joined: 22 Aug 2009 Posts: 2262
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Posted: Fri Jan 21, 2022 12:06 pm Post subject: |
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sentinel wrote: | I still don't know why the chip resets when coming out of Powersave with BOD set at 1.8V, as the supply voltage never drops below about 2.6V, even after half an hour. |
Without knowing how the power supply hardware looks like: it might be a chance of a tiny delay between Power_on signals 'power has returned' and main power output voltage is restored.
Main power PSU surely needs some rise-time, it can't be zero.
My theory applies only if Power_on is not connected to a 'power-good' signal of the PSU, but instead simply to its output supply voltage, because then pin Power_on signals already at a voltage threshold of around 1 Volt that power has returned.
In case the PSU's rise-time takes, let's say 50ms to full 3.3 Volts, then let's assume it will take 15ms to reach threshold of 1 Volt, after when Power_on will signal power has returned.
In 15ms the M168 does 120000 cycles and easily runs your main loop a few thousand times.
While doing so, it may reenable power hungry hardware (solenoid), while PSU's voltage is still in state of rising.
This in return burdens the supercap and creates the ditch, which triggers the BOD.
Of course some timed coincidence is required between waking up by _sectic and (falsely) detecting full power up condition.
Resulting in random behavior.
My shot in the dark: Add a little delay after Powersave to allow proper rise of PSU output.
Code: | '...
Powersave
Reset Watchdog
If Power_on = 1 Then waitms 100
'... |
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sentinel
Joined: 02 Feb 2009 Posts: 141 Location: Tasmania
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Posted: Fri Jan 21, 2022 2:04 pm Post subject: |
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MWS - bingo!
In my eagerness to shut down the micro when power goes off, I neglected to look closely enough at what happens when the power returns and, of course, you are absolutely correct.
When power goes off, the voltage sense line Vraw drops much faster than the 3V3 Vbat of the supercap (C3) which supplies the micro through the 100R resistor. However, when power returns, as you surmised, the sense line Vraw wakes the micro before the supercap has risen above the BOD threshold.
As you suggest, a generous delay after the Vraw sense line goes high should stop the BOD prematurely resetting the chip.
Perhaps like this:
Code: |
Do
If Supply_voltage = On Then
If Uart = Off Then
Wait 1
'Turn on BOD here
Ucsr0b.txen0 = 1
Ucsr0b.rxen0 = 1
Uart = On
Start Watchdog
End If
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Unfortunately, this can't be done with the non-Picopower version. |
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sentinel
Joined: 02 Feb 2009 Posts: 141 Location: Tasmania
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Posted: Fri Jan 21, 2022 2:26 pm Post subject: |
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O-Family, that would be true if the watchdog timeout was not re-initialised each time the WD reset carried out the instruction, but surely it's initialised to 8 seconds each time that happens and then runs the line Code: | Config Watchdog = 8192 |
I suspect that jumping to location 0000 is not a true reset, but would like to know if that is the case. |
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sentinel
Joined: 02 Feb 2009 Posts: 141 Location: Tasmania
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Posted: Fri Jan 21, 2022 2:48 pm Post subject: |
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SZTRAD, what I said was Quote: | To clarify, the BOD was not programmed while this behaviour was evident, but when it was later programmed as a test, the chip would reset every time the power was cycled, as if the supercap backup wasn't there. |
It is the BOD that causes the chip to reset every time the power comes back on. The cause of the one freeze in every ten or so power cycles is still unresolved. |
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EDC
Joined: 26 Mar 2014 Posts: 971
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Posted: Fri Jan 21, 2022 5:06 pm Post subject: |
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This is like reneving a wheel design...
If Clock is configured as User means RTC or 32768 Hz external then it can wake a uC.
uC will wake an procedure what was programmed, but this ofcourse was not a Powersave.
Then If someone start the WDT then why dont reset the WDT? This is a undependant clock... must be resetet or it cause hard reset.
This is only one of many issues I can show.
WDT interrupt must be rEEnabled.
This is a some kind of security. It was not preffered if reenabed in WDT ISR.. because of neverendin loop.
Should be used with carry.
I repeat. Once used WDT ISR should/must be reEnabled.\ |
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EDC
Joined: 26 Mar 2014 Posts: 971
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Posted: Fri Jan 21, 2022 5:21 pm Post subject: |
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WDT ISR is the last thing that can stop hardware from reset if properly used.
In the Sectic One should Reset Wathdog maybe?
Why once started WD should be stopped?.... |
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MWS
Joined: 22 Aug 2009 Posts: 2262
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Posted: Fri Jan 21, 2022 6:08 pm Post subject: |
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sentinel wrote: | As you suggest, a generous delay after the Vraw sense line goes high should stop the BOD prematurely resetting the chip. |
Judging the circuit diagram you did decouple only the M168 from other hardware.
I would suggest a delay just as long enough to bridge the gap. If you are too generous, it will use up too much charge of the supercap.
My theory was based on the idea, that the supercap can get discharged by other hardware, which is reenabled as soon the M168 gets out of sleep mode.
I believe you should have a look at the charging resistor R8.
For powering the M168 in active mode with 2mA, the resistor will create a voltage drop of 0.2V.
If additionally an output pin sources VCC, the M168 would pull this additional current from its supply, let's say 10mA for a LED, it would result in a drop of 1.2V and may create a BOD-reset.
Why not try my suggestion? While it turns on the M168 on you have 0.2V drop, only take care that no output is able to supply power whilst the time-gap till the PSU takes over. |
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O-Family
Joined: 23 May 2010 Posts: 320 Location: Japan
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