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Davide
Joined: 25 Sep 2005 Posts: 93
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Posted: Sat Nov 13, 2021 3:53 pm Post subject: Xmega - ADC with DMA and AC0 trigger |
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Hello,
I am sampling a sinewave signal with 1024 points every 3 seconds and print the values, the attached picture is what I have obtained with the signal connected to PA1 (ADC) and PA3 (AC0). It seams pretty stable.
I would like now to perform an FFT of the signal and I like a variable and convenient sampling rate.
The ADC prescaler is set at 64 which translate in ADC sampling rate of 500Khz, different sampling can be adjusted by a different prescaler but I would prefer a more flexibility option, perhaps by using a configurable timer?
Does anyone here tried to control the sampling frequency of the ADC using a timer?
Looking forward to some example.
Kind regards
Davide
[code]
$regfile = "xm128a1def.dat"
$crystal = 32000000 '32MHz
$hwstack = 64
$swstack = 40
$framesize = 40
Enable_dmach0 Alias Dma_ch0_ctrla.7
Config Portj.0 = Output
test Alias Portj.0
$lib "xmega.lib"
$external _xmegafix_clear
$external _xmegafix_rol_r1014
Config Osc = Enabled , 32mhzosc = Enabled
Config Sysclock = 32mhz
Config Sysclock = 32mhz , Prescalea = 1 , Prescalebc = 1_1
Const Xx = 255 - 6
Osc_dfllctrl = Osc_dfllctrl And Xx
Osc_dfllctrl.0 = 1
Osc_ctrl = Osc_ctrl Or 6
Bitwait Osc_status.1 , Set
Bitwait Osc_status.2 , Set
Dfllrc32m_ctrl.0 = 1
Clk_psctrl = 0
'Serial Interface to PC
Config Com1 = 115200 , Mode = Asynchroneous , Parity = None , Stopbits = 1 , Databits = 8
Open "COM1:" For Binary As #1
Print #1 , "--ADC A over DMA in 12-Bit Mode--"
'+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Const Sample_count = 1024 'Number of 12-Bit Samples (Measurement Values)
'+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Dim Channel_0(sample_count) As Integer 'Measurement Array for Channel 0
Dim Milli_volt As Single
Dim Dma_ready As Bit
Dim Dma_channel_0_error As Bit
Dim Channel_0_sample_count As Word
Dim X As Word
dim count as word
Config Aca0 = On , Hysmode = large ,HISPEED=ENABLED, Muxplus = 3 , Muxmin = 7 , Output = Enabled ,Trigger =RISING ,Scale=50
ON ACA_AC0 ISR_ACA_AC0
ENABLE ACA_AC0
' DMA Interrupt
On Dma_ch0 Dma_ch0_int
Config Dma = Enabled , Doublebuf = Disabled , Cpm = Ch01rr23 ' enable DMA, Double Buffer disabled
Config Dmach0 = Enabled , Burstlen = 2 , Chanrpt = Disabled , Tci = Lo , Eil = Lo , Singleshot = enabled , _
Sar = Burst , Sam = inc , Dar = Transaction , Dam = Inc , Trigger = &H10 , Btc = 2048 , Repeat = 0 , Sadr = Varptr(adca_ch0_res) , Dadr = Varptr(channel_0(1))
'Configure ADC of Port A in FREE running mode, pin input PA1
Config Adca = Free , Convmode = UNSIGNED , Resolution = 12bit , Dma = Ch01 , _
Reference = Intvcc , Event_mode = None , Prescaler = 64 , Sweep = Ch0 , _
Ch0_gain = 1 , Ch0_inp = SINGLE_ENDED , Mux0 = &B00001000
Config Priority = static , Vector = Application , lo = Enabled
enable Interrupts
'disable adca_ch0
disable ACA_AC0
'----------------------[Mainloop]-----------------------------------------------
Do
if Dma_ready = 1 then
Dma_ready = 0
'-------------------------------------------------------------------------------
Print #1 , Sample_count ; " Sample READY"
'Print Results to COM1
For X = 1 To Sample_count
Print #1 ,Channel_0(x)
Waitms 1
Next
end if
wait 3
enable ACA_AC0,lo
loop
End
'----------------------[Interrupt Service Routines]-----------------------------
' Dma_ch0_int is for DMA Channel ERROR Interrupt A N D for TRANSACTION COMPLETE Interrupt
' Which Interrupt fired must be checked in Interrupt Service Routine
Dma_ch0_int:
If Dma_intflags.0 = 1 Then 'Channel 0 Transaction Interrupt Flag
Set Dma_intflags.0 'Clear the Channel 0 Transaction Complete flag
Set Dma_ready
End If
If Dma_intflags.4 = 1 Then 'Channel 0 ERROR Flag
Set Dma_intflags.4 'Clear the flag
Set Dma_channel_0_error 'Channel 0 Error
End If
Return
ISR_ACA_AC0:
Set Enable_dmach0
set Portj.0
waitus 10
reset Portj.0
return
(BASCOM-AVR version : 2.0.7.8 , Latest : 2.0.8.4 ) |
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JC
Joined: 15 Dec 2007 Posts: 585 Location: Cleveland, OH
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Posted: Sun Nov 14, 2021 12:38 am Post subject: |
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Sorry, I don’t have a specific answer to your question on how to sample at variable rates at your very high sampling rate, ( 500 KSamples/Sec).
I wonder, however, what the frequency range of your input signal will be that you are going to feed to the FFT, (DFT), algorithm?
Your sample sine wave is 3.215 kHz.
In order for a sine wave signal to show up in an FFT bin, one has to sample the signal at greater that two times the frequency of the sine wave, (Nyquist-Shannon sampling theorem).
In practice, one usually samples at more than “just over” the requirement, due to rounding errors in the FFT calculations, and discontinuities in the edges of the sampling interval.
So, for a 3 KHz sine wave, one might sample at 10 K Samples / Sec, for example.
Too high a sampling rate, (i.e. too high a input bandwidth), just adds noise to the signal being processed, so there is a trade-off in terms of how fast one samples the input signal.
Your present sampling rate of 500 kHz would, therefore, seem to be very high, and much, much higher than needed to detect a 3 KHz signal in the input.
Hence the question about what is the bandwidth, or the frequency range, or the highest frequency in your input signal that you wish to detect in the FFT output?
Know that sampling the 3.215 KHz signal at 6.5 K Samples / Sec, (i.e. > 2 * 3.215), will result in the signal showing up in the FFT output.
If, however, one displayed those samples in the time domain, (O’scope), the displayed signal would look terrible! It would not look like a sine wave at all, it would have only slightly more than 2 data points per cycle of the sine wave!
If, however, on then fed that signal back through a (good) Low Pass Filter and displayed the signal on an O’Scope, one would see the original sine wave.
More Samples / cycle of the sine wave gives a nicer appearing sine wave on an O’scope, (time domain) display, if one simply plots them (without LPF’ing the signal), but it isn’t necessary to have the high sampling rate if you are only going to process the FFT output data.
If you already knew this then sorry for wasting your time!
You might also consider using canned data and an FFT, (DFT) algorithm on a PC to see the output spectrum, and more easily play with the input signal and sampling rate, etc. to see the results. Once you have the criteria firmly determined, then switch to the Xmega.
Good luck with your project!
JC |
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MWS
Joined: 22 Aug 2009 Posts: 2262
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Posted: Sun Nov 14, 2021 6:34 pm Post subject: Re: Xmega - ADC with DMA and AC0 trigger |
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Davide wrote: | Looking forward to some example. |
You mean copy, paste, execute? I fear that's not how it usually works.
A guy was already doing what you desire, sample code is in C, but he describes his approach very well and afaics every of the steps can be done with a Bascom Config command.
https://community.atmel.com/projects/xmega-event-system-timer-and-adc
In case I missed one which can't be not done via Config ..., you need to directly write to registers.
Helpful therefor can be Microchip Studio, or even an old Atmel Studio 4.1, you can create an empty project for your type of processor, compile and start the simulator.
In the I/O-view drop-down settings schow which event-connections can be used on Event system, Timer, ADC a.s.o., changing them the new register values can be looked up in the split register-view.
To start with the linked example:
Code: | CONFIG EVENT_SYSTEM = dummy, MUX0 = TCC0_OVF ' event channel 0 input for timer 0 overflow
CONFIG ADCA = Single, EVENT_CHANNEL = CH0123, EVENT_MODE=CH0, ... ' trigger AD-conversion by event on channel 0 = from timer 0 overflow
' a.s.o. |
How to do a DMA transfer you already know, and how to set up a timer too. Thus you only have to link timer and ADC-trigger via the Event channel, speed of triggering AD-conversion is controlled via Timer0.PER. |
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Davide
Joined: 25 Sep 2005 Posts: 93
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Posted: Mon Nov 15, 2021 7:28 pm Post subject: |
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Hello JC and MWS,
thanks for your great advice as usual
I tried your suggestion and it works:
Code: | Config Adca = single , Convmode = UNSIGNED , Resolution = 12bit , Dma = Ch01 , _
Reference = Intvcc , Event_mode = CH0 , Prescaler = 16 , Sweep = Ch0 , _
Ch0_gain = 1 , Ch0_inp = SINGLE_ENDED , Mux0 = &B00001000
Config Tcc0 = Freq , Prescale = 2 , Comparea = Enabled , Resolution = 16
CONFIG EVENT_SYSTEM = dummy, MUX0 = TCC0_OVF ' event channel 0 input for timer 0 overflow
TcC0_cca = &H0010 'System Clock/2*Prescaler(CCA + 1) = 32MHz/2*2(16 + 1) = 32MHz/4*65536 =470.5 Khz |
I can now change the sampling frequency freely.
Let me explain a bit my application, I need to find the relative phase between two sinewave (both at 3 KHz or 10 KHz as example) and the amplitude which drive the ADC (signal 1), the signal 2 is the reference and drive the AC.
The AC then will trigger the start of the conversion via the DMA to synchronize with the reference, the reference is at the same frequency and the same amplitude all the time.
I can successfully see the right phase difference graphically exporting the data to a spreadsheet.
My hard part is now how to do all the calculation locally, I think to choose between a FFT or Goertzel algorithm.
I will study a bit, I suspect the Goertzel algorithm maybe the best choice since I need a speedy calculation, I would prefer to stay at higher sampling rate to gain some acquisition time... I know there must be some integer relation between the sampling frequency and the signal to be detect. I did not find many example in Bascom...let see what I will obtain.
I attach few pictures to give the clue of my setup and tasks.
Please freely comment in case you have any question or advice.
BR
Davide
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MWS
Joined: 22 Aug 2009 Posts: 2262
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Posted: Tue Nov 16, 2021 10:17 am Post subject: |
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Channel sweeping ADC0..1, calculating min/max/zero from each channel data and phase-difference isn't a feasible approach? |
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Davide
Joined: 25 Sep 2005 Posts: 93
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Posted: Tue Nov 16, 2021 12:27 pm Post subject: |
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Hi MWS,
The idea looks good but I have to see how stable between readings is the phase result.
I fear the max and min value has got a jitter and noise which effect the phase calculation, maybe an averaging of the samples will help to remove a bit of noise. I have to try.
A second option could be to aqcuire with two separate ADCs with the same AC trigger. In this way the relative phase is constant even the AC has got some jitter, it require simultaneus ADC, maybe XM128 can do.
I was thinking at Goertzel algorithm since it contains a kind of filtering itself, how stable the phase output is ? Still to check it out.
I will run some test in the next days.
Have a good day.
Davide |
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Davide
Joined: 25 Sep 2005 Posts: 93
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Posted: Sat Nov 20, 2021 6:00 pm Post subject: |
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Hello,
some update about the phase measurements using the Goertzel algorithm, sampling is 200KHz, 10Khz the frequency of the signal, 100 the number of the samples.
In the picture there are several reading in sequence from the same signal, the repeatability is not very good, I think because of the Clock jitter.
By the way the phase is tracking when I change one of the two inputs accordingly.
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Davide
Joined: 25 Sep 2005 Posts: 93
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Posted: Tue Nov 30, 2021 10:11 pm Post subject: |
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Hello,
I did several test since my first post on this subject and I would like to share some result and finding along the way.
I had to change a bit my setup, instead an Xmega128a1 I switched to Xmega32A4U, just because I have a spare board with an external crystal at 16 Mhz, to gain some stability and frequency accuracy.
It turn out I had also to avoid to use the AC0 interrupt service, instead I use the wait bit function to see if the status of AC0 to start the ADC acquisition.
As reported in the last post the phase did not show stable result at first glance, I had to push higher the ADC sampling rate up to 1 Mhz (FC is 10 Khz), see the timer setting.
To reach a stability of 1-2 degree in phase (consecutive readings each 3 seconds) I also had to overlock the CPU up to 64 Mhz (PPL X4).
The Geortzel algorithm takes about 5-6 ms to show the phase result, not quickly as I would expect but acceptable for 8 bit CPU .
Overall it seams that the start of the ADC conversion is not always at the same time (AC0 trigger differently or CPU process?), any idea what is bottleneck ?
- Comparator delay time - Why not constant?
- ADC response?
- CPU reaction ?
- interrupt service?
I tried several option, the one I attach is the most stable and reliable, any idea?
Davide
Code: |
$regfile = "xm32a4Udef.dat"
$crystal =64000000 '64MHz
$hwstack = 128
$swstack = 128
$framesize = 128
$lib "xmega.lib"
'64 MHz External 16 MHz Xtal, PLL x 4
Config Osc = Enabled , Extosc = Enabled , Pllosc = enabled , Range = 12mhz_16mhz , Startup = Xtal_16kclk , Pllsource = Extclock , Plldiv2 = Disabled , Pllmul = 4
Config Sysclock = Pll , Prescalea = 1 , Prescalebc = 1_1
'Serial Interface to PC
Config Com5 = 115200 , Mode = Asynchroneous , Parity = None , Stopbits = 1 , Databits = 8
Open "COM5:" For Binary As #1
Const Sample_count = 100 ' samples
Dim Adc_buf(Sample_count) As word
Dim Coeff As double
Dim Y2 As double
Dim Y1 As double
Dim Y0 As double
Dim Real As double
Dim Imaj As double
dim phase as double
Dim Pwr As double
Dim Tmp_id As word
dim dummy as double
Dim omega as double
Dim Channel_0(sample_count) As word 'Measurement Array for Channel 0
Dim Dma_ready As Bit
Dim Dma_channel_0_error As Bit
Dim Channel_0_sample_count As Word
Dim X As Word
dim count as word
Enable_dmach0 Alias Dma_ch0_ctrla.7
Config Porte.1 = Output
test Alias Porte.1
Print #1 , "Start"
'Goertzel Algoritm constants as function of Fc (carrier frequency to be detected) and Fs (sampling frequency)
'********** 1KZ -200Khz
'Coeff= 1.999013120731
'omega= 0.031415926
'********** 10KZ - 200Khz
'Coeff= 1.920340573
'omega= 0.31415926
'********** 10KZ - 100Khz
' Coeff= 1.6180339887
' omega= 0.628318
'********** 10KZ - 400Khz
Coeff= 1.975376681
omega= 0.157079633
'********** 10KZ - 800Khz
'Coeff= 1.993834667
'omega= 0.078539816
'********** 10KZ - 1000Khz
Coeff= 1.996053457
omega= 0.062831853
Config Aca0 = On , Hysmode = small ,HISPEED=ENABLED, Muxplus = 3 , Muxmin = 7, Output = disabled ,Trigger =RISING ,Scale=50
ENABLE ACA_AC0
' DMA Interrupt
On Dma_ch0 Dma_ch0_int
Config Dma = Enabled , Doublebuf = Disabled , Cpm = Ch01rr23 ' enable DMA, Double Buffer disabled
Config Dmach0 = Enabled , Burstlen = 2 , Chanrpt = Disabled , Tci = Lo , Eil = Lo , Singleshot = enabled , _
Sar = Burst , Sam = inc , Dar = Transaction , Dam = Inc , Trigger = &H10 , Btc = 2*sample_count , Repeat = 0 , Sadr = Varptr(adca_ch0_res) , Dadr = Varptr(channel_0(1))
'Configure ADC of Port A in FREE running mode, pin input PA1
Config Adca = single , Convmode = unSIGNED , Resolution = 12bit , Dma = Ch01 , _
Reference = Intvcc , Event_mode = CH0 , Prescaler = 16 , Sweep = Ch0 , _
Ch0_gain = 1 , Ch0_inp = SINGLE_ENDED , Mux0 = &B00001000
Config TcD0 = Freq , Prescale = 4 , Comparea = Enabled , Resolution = 16
CONFIG EVENT_SYSTEM = dummy, MUX0 = TCD0_OVF ' event channel 0 input for timer 0 overflow
TcD0_cca = &H000F 'Timer for sampling the ADC - System Clock/Prescaler(CCA + 1) = 48MHz/4(15 + 1) = 64MHz/4*16 =1000 Khz
Config Priority = static , Vector = Application , lo = Enabled
enable Interrupts
'----------------------[Mainloop]-----------------------------------------------
Do
if Dma_ready = 1 then
reset test
stop Tcd0
Dma_ready = 0
disable Interrupts
'-------------------------------------------------------------------------------
' ********* Start Goertzel math *****************************************************
For Tmp_id = 1 To sample_count
Adc_buf(tmp_id) = channel_0(tmp_id)
Print #1 ,Adc_buf(tmp_id)
Next Tmp_id
'process all sample
For Tmp_id = 1 To sample_count
Y0 = Coeff * Y1
Y0 = Y0 - y2
dummy=Adc_buf(tmp_id)
Y0 = Y0 + dummy
Y2 = Y1
Y1 = Y0
Next Tmp_id
' Print#1, Y0
' Print#1, Y1
'Print#1, Y2
Real=Cos(omega)
Real = Y2 * Real
Real = Y1 - real
Imaj=Sin(omega)
Imaj = Y2 * Imaj
Pwr = Real * Real
Y0 = Imaj * Imaj
Pwr = Pwr + Y0
phase=atn2(imaj,real)
Phase=phase*57.2957795130
'Print#1, Real
'Print#1, Imaj
'Print#1, phase
Y0 = 0
Y2 = 0
Y1 = 0
Real=0
Imaj=0
Pwr=0
dummy=0
'********* end Goertzel math *****************************************************
end if
wait 3
Bitwait Aca_status.4 , reset
Bitwait Aca_status.4 , set
Set Enable_dmach0
start Tcd0
enable Interrupts
loop
End
'----------------------[Interrupt Service Routines]-----------------------------
' Dma_ch0_int is for DMA Channel ERROR Interrupt A N D for TRANSACTION COMPLETE Interrupt
' Which Interrupt fired must be checked in Interrupt Service Routine
Dma_ch0_int:
If Dma_intflags.0 = 1 Then 'Channel 0 Transaction Interrupt Flag
Set Dma_intflags.0 'Clear the Channel 0 Transaction Complete flag
Set Dma_ready
End If
If Dma_intflags.4 = 1 Then 'Channel 0 ERROR Flag
Set Dma_intflags.4 'Clear the flag
Set Dma_channel_0_error 'Channel 0 Error
End If
Return
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JC
Joined: 15 Dec 2007 Posts: 585 Location: Cleveland, OH
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Posted: Thu Dec 02, 2021 6:26 pm Post subject: |
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The Xmega series is sooo very easy to overclock, you just adjust the multiplier.
But be careful.
For a single board project for yourself overclocking isn't an issue, (assuming it works, etc.).
For a commercial product, you have to consider the risks of running the chip out of spec, (and temp ranges, and voltage ranges, and, and, and...).
At some point, as much as I love the AVR lineup, you might have to switch to an RPi Pico, or some other, faster, micro.
Know, also, that running the digital modules within the Xmega at a faster speed is very reasonable.
The actual rate limiting factor is actually, (I believe), the analog modules within the chip, where timing is very important.
The ADC, DAC, AC, and writing to the internal EEPROM are all very time sensitive.
Know, also, that even in a project that doesn't use the analog modules, or the EEPROM, there is still a clock limit above which the chip will fail.
I've run the Xmegas at 48 MHz, (room temp, 3V), without any difficulty, for the digital circuitry.
Atomic Zomie on AVRFreaks has routinely overclocked them into the 60's MHz range, my boards would not run that fast.
You could also consider a dual processor system where one XMega or XTiny or AVRDB is doing the analog work and sending the data to a second micro, an overclocked Xmega, that is only doing the (digital) math calculations.
Lastly, this is obvious once you think about it, but I got burned by this on a DDS project once...
If you are using an ISR for precise data sampling, (still some small jitter depending upon the micro's instruction being executed at the time the interrupt fires, i.e. ~ 1 -3 clock cycles), the faster you run your sampling, the greater the % of processing time you are spending in executing ISRs, and the less time your Main Loop will have for executing its work. Even if the ISRs have time to fire without overlapping on top of each other, one eventually runs out of foreground processing time.
Know, also, that there is a lot of overhead with ISR processing, saving and restoring registers. Having a fast ISR that needs to be executed at a very high rate is one example where, for this reason, it sometimes makes sense to write your own ISR in assembly, (non-trivial, if you haven't done it before!).
When you have hit a roadblock based on processing power for digital signal processing of analog signals, sometimes another approach is to figure out how to do some of the processing in hardware, to simplify the micro's processing tasks.
Good luck with your project!
JC |
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MWS
Joined: 22 Aug 2009 Posts: 2262
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Posted: Thu Dec 02, 2021 7:50 pm Post subject: |
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Davide wrote: | Overall it seams that the start of the ADC conversion is not always at the same time (AC0 trigger differently or CPU process?) |
Do you reset the timer to zero and do you clear pending timer interrupts before re-enabling interrupts? |
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Davide
Joined: 25 Sep 2005 Posts: 93
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Posted: Thu Dec 02, 2021 11:21 pm Post subject: |
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Quote: | Do you reset the timer to zero and do you clear pending timer interrupts before re-enabling interrupts? |
The code that should take care of that is:
Code: |
Bitwait Aca_status.4 , reset
Bitwait Aca_status.4 , set
Set Enable_dmach0
start Tcd0
enable Interrupts
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I stop and restart the timer, enable the interrupts after receiving the AC status , I noticed that the phase error is less then 1 - Fs sample, increasing the Fs the phase error decrease as a consequence of that.
I looks like the conversion could not start right of the same instant. |
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Davide
Joined: 25 Sep 2005 Posts: 93
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Posted: Thu Dec 02, 2021 11:28 pm Post subject: |
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You can see in the picture 6 consecutive acquisitions with a jitter of about 1 sample the Fc
[img]
[/img] |
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MWS
Joined: 22 Aug 2009 Posts: 2262
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Posted: Fri Dec 03, 2021 1:19 am Post subject: |
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1) setting the timer to zero makes sure that time from start to triggering the ADC is always the same.
2) my idea of having a timer-event or interrupt memorized, which are executed immediately after enabling the mechanism seems not to apply. |
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Davide
Joined: 25 Sep 2005 Posts: 93
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Posted: Fri Dec 03, 2021 8:27 pm Post subject: |
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Quote: | 1) setting the timer to zero makes sure that time from start to triggering the ADC is always the same.
2) my idea of having a timer-event or interrupt memorized, which are executed immediately after enabling the mechanism seems not to apply. |
1. The timer is stopped as soon the DMA complete the acquisition :
Quote: |
Do
if Dma_ready = 1 then
reset test
stop Tcd0
Dma_ready = 0
disable Interrupts
'-------------------------------------------------------------------------------
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2. I believe the bit which control the acquisition is the
I hold 3 second before restating a new acquisition, the timer is stopped 3 seconds before, I don't think we have interrupt pending waiting.... |
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MWS
Joined: 22 Aug 2009 Posts: 2262
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Posted: Sat Dec 04, 2021 7:16 pm Post subject: |
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Davide wrote: | 1. The timer is stopped as soon the DMA complete the acquisition : |
It is stopped. But unlikely at zero
If it comes to stop at value 120, then it takes less to reach top and trigger the ADC.
Thus the first sample occurs earlier than expected and it looks like the AC is jittering.
I would also re-order this:
Code: | wait 3
Bitwait Aca_status.4 , reset
Bitwait Aca_status.4 , set
Set Enable_dmach0
start Tcd0
enable Interrupts |
into:
Code: | Set Enable_dmach0
enable Interrupts
Tcd0 = 0 ' set defined start condition
wait 3
Bitwait Aca_status.4 , reset
Bitwait Aca_status.4 , set
start Tcd0 |
How about a few times oversampling climbing-algo with alternating acquisition of two channels? |
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