How to enable and disable DMA transmission ATxmega

cyklop1977 · Joined: 05 Jun 2011 Posts: 11

Hi

For the project I will use a 40kHz sine wave. It will be ultrasonic communication so the bytes will be modulated using ON/OFF. The sent byte is similar to UART. High state - generating a sin waveform, low state - no sin waveform.
I used data array + timer + DMA + DAC to generate a sine wave . I've never used DMA before and I have a problem with it .
I want to know how to turn on and off DMA just like TIMER stop/start .

MWS · Joined: 22 Aug 2009 Posts: 2262

Configuration for DMA as well for DAC is reusable, you can issue more than one config, at one you enable, at the other disable it.
As a most simple approach you can try to switch the DAC pin to input. This is a solid way to modulate PWM output in many AVRs.
If it won't work, next obvious way is to disable/enable the DAC via config.

cyklop1977 · Joined: 05 Jun 2011 Posts: 11

I tried turning off/on the DAC or TIMER and it works. Personally, I want to do it using DMA. I also want to know how DMA works. Configuration itself is not a problem, it's about the simplest DMA START/STOP control (similar to TIMER)

MWS · Joined: 22 Aug 2009 Posts: 2262

JC · Joined: 15 Dec 2007 Posts: 586 Location: Cleveland, OH

The Xmegas are such great micros.

I was just chatting with Mark this past week about some projects requiring more processing power than the usual 16 or 20 or 24 MHz AVR !

I see that you are over-clocking your Xmega at 48 MHz, (beyond the spec'd 32 MHz).
I did that, (at 48 MHz) for a DDS signal generator and for a project that was monitoring another bus.
On AVR-Freaks Atomic Zombie overclocked them at 65 or 68 (I don't recall) MHz for generating video and audio, (making it a display driver chip).
I never had reliable operations beyond 48 MHz.
You probably already know this, but the analog functions and the EEPROMs don't overclock well, just the core digital logic does.
So be careful how fast you feed the DAC, etc.
(Or at least verify that it is meeting your performance needs).

It has been many years since I looked at uC architectures, and I ought to stay out of this, but...
As you read up on DMA know that on the Xmega the DMA controller and the core processor do not both run simultaneously, (IIRC).
They still share a data bus.
What that means is that the DMA is still much faster at reading and writing data to the memory than using the core processor to R/W to an address, store the data, increment an address, and do it again.... That takes the processor many clock cycles. The DMA hardware does it much more efficiently, (faster).
But while the DMA controller is doing that, I don't think that on the Xmegas that the core processor is simultaneously running other code.

IIRC, there are other processors where the DMA controller is, essentially, running simultaneously with the core processor, and is making its memory accesses between those of the core processor.

Understanding that difference might help as you read up on how DMA works, and how it works on the XMega.

Others can correct me if I have misunderstood how the XMega DMA works.

Good luck with your project!

JC