ATMEGA4809 TCA0 Split mode PWM 100% duty?

JamesAus · Joined: 08 Aug 2007 Posts: 50 Location: Australia

Hi All,

I've been playing around with the TCA0 on the 4809 in split mode for generating >3 PWM outputs, which in itself has been a bit of a learning curve. I would like to output from 0 - 100% duty, but this is not possible, with the maximum duty being 1 cycle less than 100%. Has anyone done the same and come up with an elegant solution?

Thanks
James

(BASCOM-AVR version : 2.0.8.4 )

albertsm · Joined: 09 Apr 2004 Posts: 5920 Location: Holland

it is always a good idea to show some code.
you mean you get 0-99 ? instead of 0-100 ?

laborratte · Joined: 27 Jul 2005 Posts: 299 Location: Berlin

As I understand the datasheet you should get a 100% on time if you set the periodic (LPER and HPER) registers to &HFE and compare registers (LCMP0 ... HCMP2) to &HFF.

sorry, no possiblities to verify this in real hardware.

JamesAus · Joined: 08 Aug 2007 Posts: 50 Location: Australia

My understanding is that in split mode the high and low become completely separate 8 bit timers sharing only the clock, with period and duty able to be set independently. In the little bit of code below ramping up and down works perfectly for TCA0_CMP2H = 0 resulting in the output being off, as it should. However in the case of TCA0_CMP2H = 200 ( top count as set by TCA0_PERH ) the output is high with the exception of one clock cycle where the output goes low. This is covered in the datasheet, however I was hoping there was a simple trick to get around it.

Laborratte if CMPxH exceeds the PERH by 1 you get a constant low output, regardless of whether it's set at &HFF, &HFE or any arbitrary value below that.

I did see a post elsewhere about this suggesting to set the DDRx to set the pin as an input at / for 100% duty and use a pullup (Or internal pullup). This is not really ideal though.

laborratte · Joined: 27 Jul 2005 Posts: 299 Location: Berlin

Yes, sorry, you are right. I misssed the "Down Count Only" behaviour of split mode. And it makes sense: if the counter reaches zero output is set to low, if CMP > PER it will never set back to high.

So I don't see an automatic way as in normal upcounting single slope mode. I'm afraid you have to catch the 100% state manually and set the pin directly, either by setting the coresspondending CMP-Enable-Bit in CTRLB register of the timer - assuming the OUT register of your pin is set to high - or by inverting the pin in its control register.

I would implement a small sub for that, something like