Joined: 30 Nov 2007 Posts: 311 Location: Delano, MN
Posted: Mon Dec 02, 2019 10:24 pm Post subject: Xmega System Clock and Clock Options(RTC calibration)
Been reading the datasheet and users A manual and trying to figure out how the internal 32KHZ osc. is calibrated. Bascom version is v2.0.8.2
I see from page 80 of the Xmega A manual, that the 32KHZ int/ext osc are routed to the system clock multiplxer. Using the the following code after the system clock is configured allows the routine to the I/O pin defined below:
Code:
configPORTd.7=output
PORTCFG_CLKEVOUT = 02 'output sysclk clock on Portd.7, pg 146/147, 154-155 for bit definitions
The result is the CLKcpu on port D.7, verified with a very accurate calibration standard. I see no other way out for the 32.768khz osc. So this must be where the DFLL circuitry resides.
My question is this, how can the 32.768KHZ internal osc be monitored so that the oscillator can be adjusted as described in section 7.10.5, page 92 of the Xmega A manual? I have the calibration standards but through several days of playing around with test code to route a clock. I have only been able to do the basic 2MHZ, 32MHZ and PLL CLKcpu clock rates to an I/O pin through the CLKEVOUT. Maybe another event that I haven't discovered yet?
If I understand correctly that once the frequency is selected and stable that it is then locked in the system clock settings.
I have been able to adjust my TCC_per values to basically have the same effect. Having the hardware event counted exactly as the timer event reports.
Currently the DFLLs are being used to calibrate the internal osc but I am still off 5us in 1765mS. I know it is not a big deal, just trying to understand the calibration process and how Atmel performs this function.
You cannot post new topics in this forum You cannot reply to topics in this forum You cannot edit your posts in this forum You cannot delete your posts in this forum You cannot vote in polls in this forum You cannot attach files in this forum You cannot download files in this forum