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optimize interrupt routine with Assembly

 
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maxneo

Bascom Member



Joined: 07 Sep 2010
Posts: 35

PostPosted: Fri Jun 05, 2015 5:15 pm    Post subject: optimize interrupt routine with Assembly Reply with quote

Can this code be done in a faster way as assemler and can anyone help me with it.

If Pinb.0 = 1 Then
Tccr1b.ices1 = 0
Else
Tccr1b.ices1 = 1
End If

Many thanks Felix

(BASCOM-AVR version : 2.0.7.8 )
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MWS

Bascom Member



Joined: 22 Aug 2009
Posts: 1801

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PostPosted: Fri Jun 05, 2015 7:40 pm    Post subject: Re: optimize interrupt routine with Assembly Reply with quote

maxneo wrote:
Can this code be done in a faster way as assemler

A bit, yes. But I doubt it will solve your problem.
Quote:
and can anyone help me with it.

Show your own efforts and you may find help.
If you didn't start right now with asm, here's a most important document for Atmels:
http://www.atmel.com/Images/doc0856.pdf
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Visovian

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Joined: 31 Oct 2007
Posts: 584
Location: Czech

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PostPosted: Sat Jun 06, 2015 6:46 am    Post subject: Reply with quote

Bascom has translated your code like this: (for Mega16)
Code:
//If Pinb.0 = 1 Then
   SBIS      PINB,0            ;Skip if bit in I/O register set
   JMP       L1                ;Jump
//Tccr1b.ices1 = 0
   IN        R23,TCCR1B        ;In from I/O location
   ANDI      R23,0b10111111    ;Logical AND with immediate (clear bit R23.6)
   OUT       TCCR1B,R23        ;Out to I/O location
//Else
   JMP       L2                ;Jump

//Tccr1b.ices1 = 1
L1:
    IN        R23,TCCR1B       ;In from I/O location
    ORI       R23,0b01000000   ;Logical OR with immediate (set bit R23.6)
    OUT       TCCR1B,R23       ;Out to I/O location
L2:

I do not think it can be shorten/fasten.
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MWS

Bascom Member



Joined: 22 Aug 2009
Posts: 1801

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PostPosted: Sat Jun 06, 2015 9:16 am    Post subject: Reply with quote

Visovian wrote:
I do not think it can be shorten/fasten.

You think wrong, it simply can be shortened and fastened by 1 or 2 cycles alone by using RJMP, the full address range of JMP isn't necessary here.

This is what it takes in cycles:
Code:
SBIS    1/3
JMP     3
IN      1
ANDI    1
OUT     1
JMP     3
IN      1
ORI     1
OUT     1
' That's 7 or 9 cycles, depending on what branch is taken.

Code:
SBIS    1/2
RJMP    2
IN      1
ANDI    1
OUT     1
RJMP    2
IN      1
ORI     1
OUT     1
' Needs 6 or 7 cycles.

Code:
IN      1
ANDI    1
SBIS    1/2
ORI     1
OUT     1
' Takes constantly 5 cycles.

Assuming no other bit of the timer configuration needs to be changed, one can use fixed values, IN/ANDI/ORI isn't required then:
Code:
LDI     1
SBIS    1/2
LDI     1
OUT     1
' Needs 4 cycles

But such small gain is all peanuts and effectively not the reason, which makes the code of the TO nonfunctional.
The bigger gain is achieved, in writing the complete ISR in ASM, as then it's possible to selectively save (PUSH/POP) only used registers, which gives a benefit of estimated 60-80 cycles, depending on the rest of the ISR-code.
As long there's still Basic code mixed with ASM in an ISR, it is much more difficult to save only the used registers.

As I've already stated, it is likely a different reason the TO's code http://www.mcselec.com/index2.php?option=com_forum&Itemid=59&page=viewtopic&t=12960 won't work.
It's not possible to give a sound assessment, only given chunks of code, so it's unlikely that the TO will get a more reasonable feedback.

That's also the reason I won't write sample ASM code for the TO, if he needs help, I expect him to do his part.
Which is at minimum that he shows some compilable code, which reflects his actual idea.
Everything else is wasted time.
Not that I'm not willing to waste time, but it's senseless wasted time. Big difference Very Happy
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