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Deanus
Joined: 26 May 2006 Posts: 188 Location: Adelaide
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Posted: Mon Feb 08, 2016 5:28 am Post subject: |
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Hi Guys,
The advantage of multiple FETs in parallel is the on resistance,
Lets assume one FET has an on resistance of 0.117R
Now put three FETs in parallel, the on resistance is now 0.039R
This is a legal way to do it with FETs, with transistors, low value current sharing resistors are required.
Same with caps, One cap ESR of .2R (Equivalent Series Resistance, The smaller the better for caps)
Three caps (of the same type in parallel, total ESR is now 0.066666R, but now has a higher surge current capability.
Down side, three time the room required.
Dean |
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Evert :-)
Joined: 18 Feb 2005 Posts: 2156
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JC
Joined: 15 Dec 2007 Posts: 584 Location: Cleveland, OH
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Posted: Tue Feb 09, 2016 2:55 pm Post subject: |
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Deanus,
Good point on decreasing the Rdson.
Evert,
Great App Note on paralleling Mosfets!
Thanks for posting the link!
JC |
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techknight
Joined: 21 Apr 2008 Posts: 231
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Posted: Tue Feb 16, 2016 4:33 pm Post subject: |
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Plons wrote: | Hi laborratte !
Double buffer in Ram of the Mega8 is a good idea
Nested interrupts are not required in this Tile-design, IMO. I did the math. Even with SPI as low as 4Mhz and Buffered Serial in @ 115kbaud, the two don't interfere. Intensity variation caused by Buffered Serial In on the Scan task is less than 1%. At 150Hz refresh for the tile, thus 300Hz for the Scantask, the 3.3ms is 300 times higher than the let's say 10us for the Buffered Serial In int handler. I am convinced that's not visible.
Techknight, was the program I posted here: http://www.mcselec.com/index2.php?option=com_forum&Itemid=59&page=viewtopic&p=70826#70826 usefull to you ?
edit: fixed the link |
I had to button the project up and get it out the door... I got it working enough using 16Mhz and toying with the fractional divider, and using the 32Khz to calibrate the 32Mhz oscillator. This was to finish the job, So no, I havent tried the code yet
HOWEVER...
I am working on another design with some of your suggestions, and I am going to try this framework at that point. Thatll be implemented in my team name captions for the scoreboards that will be put in at the Seminole county sports complex this spring, So anyone who travels or lives in Florida that visits the complex will see them operating. Hopefully! |
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techknight
Joined: 21 Apr 2008 Posts: 231
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Posted: Tue Feb 16, 2016 4:44 pm Post subject: |
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JC wrote: | I noticed that transistors Q8, 10, and 17 are in parallel, presumably for increased current drive capability.
My brain is old and tired, and I understand that some FETs don't experience thermal run away like older bi-polar transistors, (their S-D current decreases as their temperature increases, instead of the other way).
That said, I didn't see the model number for the transistors in use.
It would be worth verifying their thermal run away characteristics in the data sheet.
Even a very low series resistor can help significantly with low leveling between the three.
With the wide variety of power FETs available these days I wonder if there is some advantage to using the paralleled configuration instead of a single device rated for the current required?
JC |
AO4441
I used 3 in parallel to decrease the RDS-On, But the downside, it increases the total overall gate capacitance.
This is why I chose to use the push-pull driver. Sure, the transistor voltage drops are a little harsh bringing the gate voltage lower than 5V, However, the purpose was to switch the MOSFETS on faster than if I were to use a single transistor with a pull-up.
The thought process was to decrease the transition skew caused by the gate capacitance and the discharge/charge rate. Using the transistors, it would allow the transition to become faster, reducing the potential for ghosting, and allowing me to increase the scanning speed a bit.
But, The initial design was for a 12V tile. That got reduced to 5V, So i think simple logic-level FETS with low gate capacitance would work just as well. Maybe even using an inverter gate by itself to drive the MOSFETs, open-drain or open-collector inverter IC with a pullup.
Some suggested to use the FDS4435A to replace the AO4441, but the drawback is the miller charge/gate charge plus gate capacitance is twice to three times as high, which I dont think using a simple CMOS logic gate as a driver could handle that, so the push-pull setup is still in play. Of course, I have 3 in parallel so really its about equal to one FDS4435A. |
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