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enniom
Joined: 20 Oct 2009 Posts: 537
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Posted: Mon Mar 19, 2018 4:13 am Post subject: XMEGA Operation with CPU (Almost) Sleeping? |
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This samples shows some of the features others have described in various other posts.
Demo code:
Code: | $regfile = "xm32e5def.dat"
$hwstack = 64
$swstack = 64
$framesize = 64
'$sim
$crystal = 32000000
Config Osc = Disabled , 32mhzosc = Enabled
Config Sysclock = 32mhz , Prescalea = 1 , Prescalebc = 1_1
'============================================================================
'Interrupts
'============================================================================
Config Priority = Static , Vector = Application , Lo = Enabled
'============================================================================
'Initialize
'============================================================================
Dim Payload(24) As Byte 'Host TX Payload
Payload(1) = Asc( "B")
Payload(2) = Asc( "a")
Payload(3) = Asc( "t")
Payload(4) = Asc( "V")
Payload(5) = Asc( "o")
Payload(6) = Asc( "l")
Payload(7) = Asc( "t")
Payload(8) = Asc( ":")
Payload(9) = Asc( " ")
Payload(10) = Asc( "?")
Payload(11) = Asc( "?")
Payload(12) = Asc( "V")
Payload(13) = Asc( " ")
Payload(14) = 13
Payload(15) = 10
Payload(16) = 255
Dim Bat_volt As Word At Payload(10) Overlay
Wait 5
'============================================================================
'Timer
'============================================================================
Config Tcc4 = Pwm , Prescale = 1024 , Capmodeah = Both_enabled
Tcc4_per = &HFF00
Tcc4_cca = &H4000
Stop Tcc4
On Tcc4_ovf Tcc4_isr
Enable Tcc4_ovf , Lo
'============================================================================
'Event System - Not used in this demo
'============================================================================
'Config Event_system = Dummy , _
'Mux7 = Tcc0_ovf 'TCC0 results in EVSYS_CH0MUX=&B1100_0000 - which is correct for TCC4 on E5 XMega
'============================================================================
'ADC for Battery Voltage
'============================================================================
Config Adca = Free , Convmode = Unsigned , Resolution = 12bit , Reference = Int1v , _
Prescaler = 512 , Ch0_gain = 1 , Ch0_inp = Internal , Mux0 = &B0_0010_000 , _
Dma = Ch01 , Event_mode = None 'Vcc/10
'============================================================================
'USART Interface
'============================================================================
Config Com1 = 115200 , Mode = Asynchroneous , Parity = None , Stopbits = 1 , Databits = 8
'============================================================================
'Config EDMA
'============================================================================
Dim Start_edma_usart As Byte , Start_edma_adc As Byte
Config Edma = Enabled , Doublebuf = Disabled , Cpm = Rr , Chmode = Std02 'EDMA Configured as a STANDARD Channels
'USART TX
Config Edmach2 = Enabled , Burstlen = 1 , Chanrpt = Disabled , Tci = Off , Eil = Off , Singleshot = Enabled , Trigger = &H4D , _
Btc = 15 , Sar = Transaction , Sam = Inc , Sadr = Varptr(payload(1)) , Dar = None , Dam = Fixed , Dadr = Varptr(usartc0_data)
'Using TCC4_CCA, activate ADC and tranfer values to Word Variable Batt_vol (overlayed onto payload message)
Config Edmach0 = Enabled , Burstlen = 2 , Chanrpt = Disabled , Tci = Off , Eil = Off , Singleshot = Enabled , _
Sar = Transaction , Sam = Inc , Dar = Transaction , Dam = Inc , Trigger = &H42 , Btc = 2 , Sadr = Varptr(adca_ch0_res) , Dadr = Varptr(bat_volt)
'Trigger is TCC4_CCA
Start_edma_adc = Edma_ch0_ctrla Or &B1001_0000 'Enable Channel and Transfer Request
Start_edma_usart = Edma_ch2_ctrla Or &B1001_0000
'============================================================================
'Initialize
'============================================================================
Start Tcc4
Enable Interrupts
Waitms 1
Print Chr(13) ; "---M A I N ----"
'============================================================================
'Main
'============================================================================
Do
Config Powermode = Idle
Loop
End '
'============================================================================
'Interrupt Service Routines
'============================================================================
Tcc4_isr:
Tcc4_intflags.0 = 1 ' clear interrupt flag
Edma_ch0_ctrla = Start_edma_adc
Edma_ch2_ctrla = Start_edma_usart
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albertsm
Joined: 09 Apr 2004 Posts: 5913 Location: Holland
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Posted: Tue Mar 20, 2018 9:14 pm Post subject: |
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thanks for sharing.
The E5 series is a bit puzzling to me. I do not know why atmel suddenly decided that interrupts flags must be cleared manual. And i do not see what exactly is enhanced in the DMA, but your example is a good demo that shows DMA is working without actual work from the processor. I had no idea it would work in power down mode too. _________________ Mark |
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EDC
Joined: 26 Mar 2014 Posts: 971
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Posted: Wed Mar 21, 2018 4:35 am Post subject: |
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I like Enion`s examples/trys of DMA usage examples. In my opinion the goal will be use DMA for read AVR-DOS from SD-card in the background
I was do some tests with USART in the SPI mode for that but AVR-DOS lib is shared like compiled one so no changes we can make.
There is a mention that sources can be bought/shown for those who needs it.
A couple days ago I got an idea (for try) to modify KokeKat FAT library for DMA cause it is open and maybe some backgroud moves of the DMA can be done |
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albertsm
Joined: 09 Apr 2004 Posts: 5913 Location: Holland
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Posted: Wed Mar 21, 2018 9:58 am Post subject: |
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the AVR-DOS drivers are open and can be modified. if you study dos/fat you will see that it make no sense to change avr-dos but that you can change the driver. _________________ Mark |
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enniom
Joined: 20 Oct 2009 Posts: 537
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Posted: Fri Mar 23, 2018 11:43 pm Post subject: |
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Hi Mark,
Thinking about your question about what is "special" about the Enhanced DMA in E Series XMEGA (versus the DMA provided in A Series), I can provide 2 comments:
1. The EDMA tries to provide 4 DMA channels (like the A Series), but in a "small" and inexpensive chip. But to get 4 channels, we need to work with Peripheral DMA channels instead of Standard DMA. As far as I can see, Peripheral channels are OK in some functions and not others. For example, they work well for USART Receiving, but do not work for USART Transmitting.
2. The EDMA provides a Byte or Word search function where a SRAM Array can be searched for a match. The following code works for searching a byte:
Code: | $regfile = "xm32e5def.dat"
$hwstack = 200
$swstack = 200
$framesize = 200
$crystal = 32000000
Config Osc = Disabled , 32mhzosc = Enabled ' 32 MHz enabled
Config Sysclock = 32mhz , Prescalea = 1 , Prescalebc = 1_1 'use 32 MHz
Config Priority = Static , Vector = Application , Lo = Enabled , Med = Enabled
'====Config USART ====
Config Com1 = 115200 , Mode = Asynchroneous , Parity = None , Stopbits = 1 , Databits = 8
Dim Payload(60) As Byte , Dummy(60) As Byte
Dim I As Byte , Match_ok As Byte , Match_key As Byte
For I = 1 To 60
Payload(i) = I
Next
Payload(8) = &H26
Payload(15) = &H27
'====Config DMA ====
Config Edma = Enabled , Doublebuf = Disabled , Cpm = Rr , Chmode = Std02 'Yes
'Config as standard channel and use manual trigger to start search
Config Edmach0 = Enabled , Burstlen = 1 , Chanrpt = Enabled , Tci = Lo , Eil = Off , Singleshot = Enabled , _
Trigger = &H00 , Btc = 60 , _
Sar = Transaction , Sam = Inc , Sadr = Varptr(payload(1)) , Dar = Transaction , Dam = Inc , Dadr = Varptr(dummy(1))
On Edma_ch0 Edmach_rx_isr 'Interrupt MUST be cleared in ISR!!!!!
Edma_ch0_ctrla.7 = 0 'disable channel
'Set up byte search for Standard EDMA Channel with bits 2..0 of DESTADDRCTRL
Edma_ch0_destaddrctrl.2 = 1 : Edma_ch0_destaddrctrl.1 = 0 : Edma_ch0_destaddrctrl.0 = 0
'Set up byte mask to match
Match_key = &H26
Edma_ch0_destaddrl = Match_key 'L=data
Edma_ch0_destaddrh = Match_key 'H=mask
Enable Interrupts
'====M a i n ====
Do
Edma_ch0_ctrla = Edma_ch0_ctrla Or &B10010000 'EDMA must be re-enabled with each check
I = Edma_ch0_addrl + 1
Waitus 10
If Match_ok = 1 Then 'Match throws interrupt; Clearing interrupt flag restarts search
Print "Match at array index: " ; I
Edma_ch0_ctrla.7 = 0 'disable channel
Match_key = &H27
Edma_ch0_destaddrl = Match_key 'L=data
Edma_ch0_destaddrh = Match_key 'H=mask
Match_ok = 0
Wait 1
End If
Loop
End
Edmach_rx_isr:
If Edma_intflags.0 = 1 Then 'DMA Channel 0 Transaction Interrupt
Edma_intflags.0 = 1 'Clear Interrupt
Match_ok = 1 'set flag
End If
Return
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BUT, the search feature has some significant problems:
- it must be done with the CPU fully active and, as far as I can determine, only on SRAM variables (not Flash or EEPROM),
- for each byte searched without a match, the channel is disabled has to be re-enabled by EDMA_CH0_CTRLA = EDMA_CH0_CTRLA Or &B10010000
- a match throws the EDMA Interrupt, but unless the index is saved before the interrupt, the value of the index is reset to 0 once the interrupt occurs.
So, after spending time to figure this out, I cannot see much use for the Enhanced DMA SRAM search feature.
[PS: to tried to see if the match feature could be used in a way similar to Bytematch on a USART receiving channel. But, as far as I can determine, match only works on SRAM array variables.]
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